Funding News: We Just Raised $6 Million to Reimagine Analog Chip Design
We Just Raised $6 Million to Make Analog Chip Design Smarter with AI
We’ve got some exciting news to share — we’ve raised $6 million in seed funding to bring generative AI into one of the toughest and most overlooked parts of semiconductor engineering: analog chip design.
The round was led by UTEC (University of Tokyo Edge Capital Partners), with support from Endiya Partners and Exfinity Venture Partners. Their belief in what we’re building means a lot — because what we’re building could change how the world designs the very chips that power today’s AI revolution.
Why We’re Doing This
If you’ve ever worked in chip design, you know that digital design is automated — there are powerful EDA tools from companies like Synopsys and Cadence that take care of most of the heavy lifting.
But analog chips? That’s a whole different story. They deal with real-world signals — sound, light, temperature, power — and designing them still feels like an art form. Engineers spend months (sometimes years) fine-tuning transistor-level details, running simulations, and repeating the process over and over.
We’ve lived through those cycles ourselves. And we thought: There has to be a better way.
What We’re Building
We’re building an AI-powered copilot for analog design — a kind of intelligent assistant that works right inside your existing design tools.
Our AI can:
- Understand your design specs, circuit diagrams, and simulation results
- Answer your questions in plain language
- Suggest alternative architectures or performance trade-offs
- Automatically review your designs for inconsistencies
It’s trained on publicly available data — things like research papers and patents — and can run entirely on your local setup, so your design data stays private and secure.
Early results are promising: we think our AI can help cut analog design cycles by half — or even two-thirds.
What’s Next
We’re gearing up for early customer trials by March 2026, focusing on a few lead partners before expanding to a broader launch.
Our first users will include global chip companies with design teams in India, as well as Japanese semiconductor firms — both groups already deeply interested in what we’re doing.
“Analog design today is still a very manual, iterative process. What we’re building will make those cycles faster, more systematic, and less dependent on large teams.”
— Ashish Lachhwani, Co-founder & Chief Business Officer
“Having gone through those long, manual design cycles ourselves, we knew there had to be a better way. Generative AI gives us the tools to finally make analog design faster and more intelligent.”
— Gireesh Rajendran, Co-founder & CEO
Bridging Two Worlds
We’re proud to be building this out of India’s growing AI ecosystem, while working closely with Japan’s world-class hardware and semiconductor industry.
“Maieutic’s technology could fundamentally compress design cycles and redefine productivity for chip engineers worldwide.”
— Kiran Mysore, Principal, UTEC
That’s exactly the kind of impact we’re aiming for — helping engineers everywhere build better chips, faster.
The Road Ahead
We founded Maieutic in April 2025, but our journey started years ago — when our team built Steradian Semiconductors, an imaging radar startup later acquired by Renesas Electronics. That experience taught us what it takes to push the boundaries of chip design.
Now, with the rise of AI, we finally have the technology to bring that vision to life.
We’re just getting started — and we can’t wait to show you what’s next.
Stay tuned for updates as we move toward early trials and our first product launch in 2026.